Non-volatile memory devices, including erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM), have the capability of maintaining stored information after the power supply is removed. One type of EPROM includes a single transistor cell having a control gate and a floating gate, the floating gate being between the control gate and a silicon substrate. An EEPROM cell generally employs two transistors.
The conventional method of forming a split gate non-volatile memory cell in a semiconductor device is depicted in FIGS. 1A to 1D. Referring to FIG. 1A, a semiconductor substrate 10 has a cell array region a, a boundary region b, and a peripheral logic region (not shown). A field oxide layer 12 is formed in and on semiconductor substrate 10. A gate oxide layer 13 is formed over an active region of the cell array region a. To manufacture a floating gate of a transistor, a first conductive or polysilicon layer 14 is formed on the field oxide layer 12 and the gate oxide layer 13. An interpoly oxide layer 16 is disposed on the first polysilicon layer 14. The first polysilicon layer 14 and the interpoly oxide layer 16 are patterned to produce a terminal edge 15, which is over the boundary region b. For control gates of memory cells and gates of transistors in the peripheral logic region, a second conductive or polysilicon layer 18 is formed over the semiconductor substrate 10. A self aligned etching mask 20, e.g., a photoresist pattern, is deposited on selected portions of the second polysilicon layer 18. Referring to FIG. 1B, portions of the first and second polysilicon layers 14 and 18 and the interpoly oxide layer 16, which are not protected by the mask 20, are removed to produce a split gate 22. The split gate 22 includes a control gate 18a and a floating gate 14a, separated by a remaining portion 16a of the interpoly oxide layer. Thereafter, the mask 20 is removed. The remaining structure additionally includes conductive layers 18b and 14b, and an interpoly oxide layer 16b overlying boundary region b.
Referring to FIG. 1C, a second mask or photoresist layer 24 is selectively formed on the resulting structure of FIG. 1B. The photoresist layer 24 does not cover a selected portion 19 of the conductive layer 18b. The exposed portion 19 of the second conductive layer 18 is then etched to form the gates (not shown) of transistors in the peripheral logic region.
The second photoresist layer 24 is removed to produce the structure illustrated in FIG. 1D. As shown in FIG. 1D, an electrically conductive structure 26, which includes the conductive layers 14b and 18b and interpoly oxide layer 16b, overlies boundary region b. The conductive structure 26 can cause a local charge-up phenomenon during the photolithography process. The charge-up can produce an arc or electrical discharge that causes structural damage or creates polysilicon particle contamination. Accordingly, a process is desired which eliminates the formation of a conductive layer overlying the boundary region b.